1. Field of the Invention
This invention relates to a semiconductor read-only memory device (ROM), and more particularly it relates to a semiconductor ROM using two kinds of MOS type field effect mode transistors (MOSFET) as memory elements storing either one of two different values of information.
2. Description of the Prior Art
FIG. 1 is a circuit diagram showing only a primary portion of a typical conventional ROM. A ROM memory array includes a good number of memory banks only two of which are illustrated as generally designated by 1 and 2 in FIG. 1. The memory bank 1 includes serially connected MOSFET's 11-14 for storage and the memory bank 2 includes serially connected MOSFET's 21-24 for storage. Of those MOSFET's the MOSFET's 12, 14 and 23 are of the depletion type and the remaining MOSFET's 11, 13, 14, 21, 22 and 24 are of the enhancement type. The gates of the respective MOSFET's are connected to terminals 71-74 and 81-84 to receive its corresponding memory selection signals. One end of a series circuit of the MOSFET's 71-74 is connected to a bit line 7 and one end of the counterpart of the MOSFET's 81-84 is connected to a bit line 8. The bit lines 7 and 8 have bit line capacitors 3 and 4, respectively. Each bit line has its one end connected to a charging circuit 5 for charging the bit line and its other end connected to a readout circuit 6, respectively.
Assuming for the convenience of explanation only that all of the MOSFET's 11-14 and 21-24 are of the n channel type, the following will set forth operation of the ROM of FIG. 1.
First of all, consideration will be given to the situation that the memory selection signal terminals 71 and 81 are held at a low level "L" (e.g. approximately OV in a system of 5 V of power supply voltage) and all of the remaining memory selection signal terminals are held at a high level "H" (e.g. approximately 5 V in a system of 5 V of power supply voltage). The bit line capacitors 3 and 4 are charged through the charging circuit 5. Since in this case the memory MOSFET's 11 and 21, which are supplied at respective gates thereof with the "L" signal, are both of the enhancement type, these MOSFET's stand in the off state. The gates of the remaining memory MOSFET's are supplied with the "H" signal and all stand in the on state whether they are of the depletion type or the enhancement type. With the memory MOSFET's 11 and 21 in the off state, the charges on the bit line capacitors 3 and 4 are not discharged and the readout circuit 6 senses a "H" potential at both the memory banks 1 and 2.
Then, for example, the memory selection signal terminals 72 and 82 are brought to a "L" level and the remaining memory selection signal terminals to a "H" level. The bit line capacitors 3 and 4 are charged. Under these circumstances the memory MOSFET's 12 and 22 which are supplied with the "L" signal are in the on state and off state, respectively, because the former is of the depletion type and the latter of the enhancement type. The remaining memory MOSFET's receiving at its gates the "H" signal stand in the on state whether they are of the depletion type or the enhancement type. The charge on the bit line capacitor 4 is not discharged due to the memory MOSFET 22 in the off state. The readout circuit 6, therefore, senses the "H" potential for the memory bank 2. On the contrary, with all of the memory MOSFET's 11-14 in the memory bank 1 in the on state, the charge on the bit line capacitor 3 is discharged therefrom and the readout circuit 6 senses the "L" potential for the memory bank 1.
In this manner, the "H" potential is sensed upon selection of the enhancement type memory MOSFET and the "L" potential is sensed upon selection of the depletion type memory MOSFET. It will be understood that ROM operation is expected provided that these potentials correspond to "1" and "0" bits of information.
To ensure high speed performance with the above described ROM arrangement, it is required to sufficiently lower the on-resistance of the depletion type memory MOSFET's when the gate voltage is "L" and to shorten the discharge time of the bit line capacitors. This implies that ion injection to the channel regions of the depletion type memory MOSFET's should be carried out in a separate step form ion injection to depletion type MOSFET's in peripheral logic circuits, resulting in increasing the number of manufacturing steps. Another outstanding problem is that manufacture is time-consumptive because of the need to form the gates after completion of channel doping.